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products and specifications discussed herein ar e subject to change by micron without notice. 128mb: x16, x32 mobile sdram features pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_1.fm - rev. l 10/07 en 1 ?2001 micron technology, inc. all rights reserved. mobile sdram mt48lc8m16lf, mt48v8m16lf, mt48lc4m32lf, mt48v4m32lf features ? temperature-compensated self refresh (tcsr) ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operatio n; column address can be changed every clock cycle ? internal banks for hiding row access/precharge ? programmable burst lengths: 1, 2, 4, 8, or full page ? auto precharge, includes co ncurrent auto precharge, and auto refresh modes ? self refresh mode; standard and low power ? 64ms, 4,096-cycle refresh (15.6s/row) ? lvttl-compatible inputs and outputs ? low voltage power supply ? partial-array self refresh (pasr) power-saving mode notes: 1. x16 only. 2. x32 only. 3. contact micron for availability. options mark ?v dd /v dd q ? 3.3v/3.3v lc ? 2.5v/2.5?1.8v v ? configurations ? 8 meg x 16 (2 meg x 16 x 4 banks) 8m16 ? 4 meg x 32 (1 meg x 32 x 4 banks) 4m32 ? package/ball out ? 54-ball vfbga (8mm x 8mm) 1 f4 ? 54-ball vfbga (8mm x 8mm) 1 pb-free b4 ? 90-ball vfbga (8mm x 13mm) 2 f5 ? 90-ball vfbga (8mm x 13mm) 2 pb-free b5 ? 54-pin tsop ii (400 mil) tg 3 ? 54-pin tsop ii (400 mil) pb-free p 3 ? timing (cycle time) ? 7.5ns @ cl = 3 (133 mhz) -75m 3 ? 8ns @ cl = 3 (125 mhz) -8 ? 10ns @ cl = 3 (100 mhz) -10 3 ?temperature ? commercial (0c to +70c) none ? industrial (?40c to +85c) it ? extended (?25c to +75c) xt 3 ?design revision :g part number example: mt48v8m16lfb4-8:g table 1: configurations 8 meg x 16 4 meg x 32 configuration 2 meg x 16 x 4 banks 1 meg x 32 x 4 banks refresh count 4k 4k row addressing 4k (a0?a11) 4k (a0?a11) bank addressing 4 (ba0, ba1) 4 (ba0, ba1) column addressing 512 (a0?a8) 256 (a0?a7) table 2: key timing parameters cl = cas (read) latency speed grade clock frequency access time t rcd t rp cl = 1 cl = 2 cl = 3 -75m 133 mhz ? ? 5.4 19ns 19ns -8 125 mhz ? ? 7ns 20ns 20ns -10 100 mhz ? ? 7ns 20ns 20ns -75m 100 mhz ? 6 ? 19ns 19ns -8 100 mhz ? 8ns ? 20ns 20ns -10 83 mhz ? 8ns ? 20ns 20ns -8 50 mhz 19ns ? ? 20ns 20ns -10 40 mhz 22ns ? ? 20ns 20ns
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobiletoc.fm - rev. l 10/07 en 2 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram table of contents table of contents fbga part marking decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 pin/ball assignments and descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 burst length (bl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 cas latency (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 write burst mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 operating mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 temperature-compensated self refresh (tcsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 partial-array self refresh (pasr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 command inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 no operation (nop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 active. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 auto refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 self refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 bank/row activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 clock suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 burst read/single write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 read with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 write with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 temperature and thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobilelof.fm - rev. l 10/07 en 3 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram list of figures list of figures figure 2: functional block diagram 8 meg x 16 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: functional block diagram 4 meg x 32 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 4: 90-ball fbga pin assignments (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: 54-pin tsop pin assignments (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 6: 54-ball vfbga pin assignments (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 7: mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 8: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 9: extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 10: activating a specific row in a specific bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 11: example: meeting trcd (min) when 2 < trcd (min)/tck< 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 12: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 13: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 14: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 15: random read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 16: read-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 17: read-to-write with extra clock cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 18: read-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 19: terminating a read bu rst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 20: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 21: write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 22: write-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 23: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 24: write-to-read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 25: write-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 26: terminating a write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 27: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 28: power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 29: clock suspend during write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 30: clock suspend during read burs t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 31: read with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 32: read with auto precharge interr upted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 33: write with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 34: write with auto precharge interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 35: example temperature test point location, 54-pin tsop : top view . . . . . . . . . . . . . . . . . . . . . . . . . . .5 0 figure 36: example temperature test point location, 54-ball vfbg a: top view . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 37: example temperature test point location, 90-ball vfbg a: top view . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 38: initialize and load mode regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 39: power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 40: clock suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 41: auto refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 42: self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 43: read ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 44: read ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 45: single read ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 46: single read ? with auto precha rge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 figure 47: alternating bank read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 48: read ? full-page burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 49: read ? dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 50: write ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 51: write ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 52: single write ? without auto prec harge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 figure 53: single write ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 figure 54: alternating bank writ e accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 55: write ? full-page burs t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 figure 56: write ? dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 figure 57: 54-ball fbga, ?f4/b4? package (x16 device), 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobilelof.fm - rev. l 10/07 en 4 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram list of figures figure 58: 90-ball fbga, ?f5/b5? package (x 32 device), 8mm x 13mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 figure 59: 54-pin plastic tsop (4 00 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobilelot.fm - rev. l 10/07 en 5 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram list of tables list of tables table 1: configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: ball descriptions: 54-b all vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 4: ball descriptions: 90-b all vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 5: pin descriptions: 54-pin tsop (x16 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 6: burst definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 7: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 8: truth table ? commands and dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 9: truth table ? cke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 10: truth table ? current state bank n , command to bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 11: truth table ? current state bank n, command to bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 12: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 13: temperature limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 14: thermal impedance simulated values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 15: dc electrical characteristics and operating conditions (lc version). . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 16: dc electrical characteristics and operating conditions (v version) . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 17: electrical characteristics and re commended ac operating conditions . . . . . . . . . . . . . . . . . . . . . . .52 table 18: ac functional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 19: i dd specifications and conditions (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 20: i dd 7 self refresh current options (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 21: i dd specifications and conditions (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 22: i dd 7 self refresh current options (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 23: capacitance (fbga pacakge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 24: capacitance (tsop pacakge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 6 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram fbga part marking decoder figure 1: 128mb sdram part numbers notes: 1. not all speeds and configurations are available. 2. contact micron for availability. fbga part marking decoder due to space limitations, fbga-packaged components have an abbreviated part marking that is different from the part number. micron?s new fbga part marking decoder makes it easier to understand th at part marking. visit the web site at www.micron.com/decoder . general description the micron ? 128mb sdram device is a high-speed cmos, dynamic random access memory containing 134,217,728 bits. it is in ternally configured as a quad-bank dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the x16?s 33,554,432-bi t banks is organized as 4,096 rows by 512 columns by 16 bits. each of the x32?s 33,554, 432-bit banks is organized as 4,096 rows by 256 columns by 32 bits. read and write accesses to the sdram are bu rst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0?a11 select the row). the address bits registered coincident with the read or write command are used to select the star ting column location for the burst access. the sdram provides for programmable read or write burst lengths (bl) of 1, 2, 4, or 8 locations, or the full page, with a burst te rminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. - configuration mt4 8 package speed t emperature configuration 8 meg x 16 4 meg x 32 8m16 4m32 package 54-ball vfbga (8 x 8mm) 54-ball vfbga (8 x 8mm) lead-free 90-ball vfbga (8 x 13mm) 90-ball vfbga (8 x 13mm) lead-free 54-pin tsop ii (400 mil) 54-pin tsop ii (400 mil) lead-free it xt operating t emp standard industrial t emp extended t emp example part number: mt48v4m32lff5-10xt voltage ( v dd /v dd q ) 3.3v/ 3.3v 2.5v / 2.5v?1.8v lc v v dd / v dd q l f f4 b4 f5 b5 tg 2 p 2 revision :g rev revision speed grade t ck = 7.5ns, cl = 3 t ck = 8ns, cl = 3 t ck = 10ns, cl = 3 -75m 2 -8 -10 2
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 7 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram general description the 128mb sdram device uses an internal pipelined architecture to achieve high-speed operation. this architecture is compatible with the 2 n rule of prefetch architectures, but it also enables the column address to be changed on every clock cycle to achieve a high- speed, fully random access. precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless high-speed, random-access operation. the 128mb sdram device is designed to op erate in 3.3v or 2.5v low-power memory systems. the 2.5v version is compatible with 1.8v i/o interface. an auto refresh mode is provided along with a power-saving, powe r-down mode. all inputs and outputs are lv t tl -c om pati b le. sdrams offer substantial advances in dr am operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to inte rleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. figure 2: functional block diagram 8 meg x 16 sdram 12 ras# cas# row- address mux clk cs# we# cke control logic column- address counter/ latch mode register 9 command decode a0-a11, ba0, ba1 dqml, dqmh 12 address register 14 512 (x16) 4,096 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (4,096 x 512 x 16) bank0 row- address latch & decoder 4096 sense amplifiers bank control logic dq0- dq15 16 data input register data output register 16 12 bank1 bank2 bank3 12 9 2 2 2 2 refresh counter 16
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 8 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram general description figure 3: functional block diagram 4 meg x 32 sdram 12 ras# cas# clk cs# we# cke 8 a0?a11, ba0, ba1 dqm0? dqm3 14 256 (x32) 4096 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (4,096 x 256 x 32) bank0 row- address latch & decoder 4,096 sense amplifiers bank control logic dq0? dq31 32 data input register data output register 32 bank1 bank0 bank2 bank3 12 8 2 4 4 2 refresh counter 12 12 mode register control logic command decode row- address mux address register column- address counter/ latch 32
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 9 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram pin/ball assignments and descriptions pin/ball assignments and descriptions figure 4: 90-ball fbga pin assignments (top view) 1234 6789 5 dq26 dq28 v ss q v ss q v dd q v ss a4 a7 clk dqm1 v dd q v ss q v ss q dq11 dq13 dq24 v dd q dq27 dq29 dq31 dqm3 a5 a8 cke nc dq8 dq10 dq12 v dd q dq15 v ss v ss q dq25 dq30 nc a3 a6 nc a9 nc v ss dq9 dq14 v ss q v ss v dd v dd q dq22 dq17 nc a2 a10 nc ba0 cas# v dd dq6 dq1 v dd q v dd dq21 dq19 v dd q v dd q v ss q v dd a1 a11 ras# dqm0 v ss q v dd q v dd q dq4 dq2 dq23 v ss q dq20 dq18 dq16 dqm2 a0 ba1 cs# we# dq7 dq5 dq3 v ss q dq0 a b c d e f g h j k l m n p r
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 10 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram pin/ball assignments and descriptions figure 5: 54-pin tsop pin assignments (top view) notes: 1. the # symbol indicate s signal is active low. figure 6: 54-ball vfbga pin assignments (top view) v dd dq0 v dd q dq1 dq2 vssq dq3 dq4 v dd q dq5 dq 6 vssq dq7 v dd dqml we# c a s # ra s # cs # ba0 ba1 a10 a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 6 17 18 19 20 21 22 23 24 25 2 6 27 54 53 52 51 50 49 48 47 4 6 45 44 43 42 41 40 39 38 37 3 6 35 34 33 32 31 30 29 28 vss dq15 vssq dq14 dq13 v dd q dq12 dq11 vssq dq10 dq9 v dd q dq8 vss n c dqmh c lk c ke n c a11 a9 a8 a7 a 6 a5 a4 vss x 16 x 16 a b c d e f g h j 1 2 3 4 5 6 7 8 top view (ball down) v ss dq14 dq12 dq10 dq8 udqm nc/a12 a8 v ss dq15 dq13 dq11 dq9 nc clk a11 a7 a5 v ss q v dd q v ss q v dd q v ss cke a9 a6 a4 v dd q v ss q v dd q v ss q v dd cas# ba0 a0 a3 dq0 dq2 dq4 dq6 ldqm ras# ba1 a1 a2 v dd dq1 dq3 dq5 dq7 we# cs# a10 v dd 9
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 11 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram pin/ball assignments and descriptions table 3: ball descriptions: 54-ball vfbga 54-ball vfbga symbol type description f2 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of cl k. clk also increm ents the internal burst counter and controls the output registers. f3 cke input clock enable: cke activates (high) an d deactivates (low) the clk signal. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank), or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke become s asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing lo w standby power. cke may be tied high. g9 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands ar e masked when cs# is registered high, but read/write burst s already in progress w ill continue and dqm will retain its dq mask capability while cs# remains high. cs# provides for external bank selection on sy stems with multiple banks. cs# is considered part of the command code. f7, f8, f9 cas#, ras#, we# input command inputs: cas#, ras#, and we# (along with cs#) define the command being entered. e8, f1 ldqm, udqm input input/output mask: dqm is sampled hi gh and is an input mask signal for write accesses and an output enable sign al for read accesses. input data is masked during a write cycle. the ou tput buffers are placed in a high-z state (2-clock latency) during a re ad cycle. ldqm corresponds to dq0? dq7, and udqm corresponds to dq8?dq15. ldqm and udqm are considered same state when referenced as dqm. g7, g8 ba0, ba1 input bank address input(s): ba0 and ba1 define to which bank the active, read, write, or precharge command is being applied. these pins also provide the op-code during a load mode register command. h7, h8, j8, j7, j3, j2, h3, h2, h1, g3, h9, g2 a0?a6 a7?a11 input address inputs: a0?a11 are sampled during the active command (row- address a0?a11) and read/write co mmand (column-address a0?a8; with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether all banks are to be precharged (a10 high) or bank select ed by ba0, ba1 (low). the address inputs also provide the op-code during a load mode register command. a8, b9, b8, c9, c8, d9, d8, e9, e1, d2, d1, c2, c1, b2, b1, a2 dq0?dq5 dq6?dq11 dq12?dq15 i/o data input/output: data bus. e2, g1 nc ? no connect: these pins should be left unconnected. g1 is a no connect for this part but may be used as a12 in future designs. a7, b3, c7, d3 v dd q supply dq power: isolated dq power on the die to improve noise immunity. a3, b7, c3, d7 v ss q supply dq ground: isolated dq power on the die to improve noise immunity. a9, e7, j9 v dd supply power supply: voltage dependant on option. a1, e3, j1 v dd supply ground.
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 12 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram pin/ball assignments and descriptions table 4: ball descriptions: 90-ball vfbga 90-ball fbga symbol type description j1 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of cl k. clk also increm ents the internal burst counter and controls the output registers. j2 cke input clock enable: cke activates (high) an d deactivates (low) the clk signal. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank), or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke become s asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing lo w standby power. cke may be tied high. j8 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands ar e masked when cs# is registered high, but read/write burst s already in progress w ill continue and dqm will retain its dq mask capability while cs# remains high. cs# provides for external bank selection on sy stems with multiple banks. cs# is considered part of the command code. j9, k7, k8 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. k9, k1, f8, f2 dqm0?3 input input/output mask: dqm is sampled hi gh and is an input mask signal for write accesses and an output enable sign al for read accesses. input data is masked during a write cycle. the ou tput buffers are placed in a high-z state (2-clock latency) during a re ad cycle. dqm0 corresponds to dq0? dq7, dqm1 corresponds to dq8? dq15, dqm2 corresponds to dq16? dq23, and dqm3 corresponds to dq24 ?dq31. dqm0?3 are considered same state when referenced as dqm. j7, h8 ba0, ba1 input bank address input(s): ba0 and ba1 define to which bank the active, read, write, or precharge command is being applied. these pins also provide the op-code during a load mode register command. g8, g9, f7, f3, g1, g2, g3, h1, h2, j3, g7, h9 a0?a5 a6?a11 input address inputs: a0?a11 are sampled during the active command (row- address a0?a11) and read/write co mmand (column-address a0?a7; with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether all banks are to be precharged (a10 high) or bank select ed by ba0, ba1 (low). the address inputs also provide the op-code during a load mode register command. r8, n7, r9, n8, p9, m8, m7, l8, l2, m3, m2, p1, n2, r1, n3, r2, e8, d7, d8, b9, c8, a9, c7, a8, a2, c3, a1, c2, b1, d2, d3, e2 dq0?dq5 dq6?dq11 dq12?dq17 dq18?dq23 dq24?dq29 dq30?dq31 i/o data input/output: data bus. e3, e7, h3, h7, k2, k3 nc ? no connect: these pins should be left unconnected. h3 is a no connect for this part, but may be used as a12 in future designs. b2, b7, c9, d9, e1, l1, m9, n9, p2, p7 v dd q supply dq power: isolated dq power on the die to improve noise immunity. b8, b3, c1, d1, e9, l9, m1, n1, p3, p8 v ss q supply dq ground: isolated dq power on the die to improve noise immunity. a7, f9, l7, r7 v dd supply power supply: voltage dependant on option. a3, f1, l3, r3 v ss supply ground.
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 13 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram pin/ball assignments and descriptions table 5: pin descriptions: 54-pin tsop (x16 only) 54-pin tsop symbol type description 38 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of cl k. clk also increm ents the internal burst counter and controls the output registers. 37 cke input clock enable: cke activates (high) an d deactivates (low) the clk signal. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank), or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke become s asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing lo w standby power. cke may be tied high. 19 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands ar e masked when cs# is registered high, but read/write burst s already in progress w ill continue and dqm will retain its dq mask capability while cs# remains high. cs# provides for external bank selection on sy stems with multiple banks. cs# is considered part of the command code. 16, 17, 18 we#, cas#, ras# input command inputs: we#, cas#, and ras# (along with cs#) define the command being entered. 15, 39 dqml, dqmh input input/output mask: dqm is sampled hi gh and is an input mask signal for write accesses and an output enable sign al for read accesses. input data is masked during a write cycle. the ou tput buffers are placed in a high-z state (2-clock latency) during a re ad cycle. dqm0 corresponds to dq0? dq7, dqm1 corresponds to dq8? dq15, dqm2 corresponds to dq16? dq23, and dqm3 corresponds to dq 24?dq31. ldqm corresponds to dq0?dq7, and udqm co rresponds to dq8?dq15. ldqm and udqm are considered same state when referenced as dqm. 20, 21 ba0, ba1 input bank address input(s): ba0 and ba1 define to which bank the active, read, write, or precharge command is being applied. these pins also provide the op-code during a load mode register command. 23, 24, 25, 29, 30, 31, 32, 33, 34, 22, 35 a0?a5 a6?a11 input address inputs: a0?a11 are sampled during the active command (row- address a0?a11) and read/write co mmand (column-address a0?a7; with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether all banks are to be precharged (a10 high) or bank select ed by ba0, ba1 (low). the address inputs also provide the op-code during a load mode register command. 2, 4, 5, 7, 8, 10, 11, 13, 42, 49, 45, 47, 48, 50, 51 dq0?dq7 dq8?dq15 i/o data input/output: data bus (x16 only). 36, 40 nc ? no connect: these pins should be left unconnected. pin 36 is a no connect for this part, but may be used as a12 in future designs. 3, 9, 43, 49 v dd q supply dq power: isolated dq power on the die to improve noise immunity. 6, 12, 46, 52 v ss q supply dq ground: isolated dq power on the die to improve noise immunity. 1, 14, 27 v dd supply power supply: voltage dependant on option. 28, 41, 54 v ss supply ground.
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 14 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram functional description functional description in general, the 128mb sdrams (2 meg x 16 x 4 banks and 1 meg x 32 x 4 banks) are quad- bank drams that operate at 3.3v or 2.5v and include a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the x16?s 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. each of the x32?s 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits. read and write accesses to the sdram are bu rst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the ba nk and row to be accessed (ba0 and ba1 select the bank, a0?a11 select the row). the address bits (x16: a0?a8; x32: a0?a7) regis- tered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. initialization sdrams must be powered up and initiali zed in a predefined manner. operational procedures other than those specified may resu lt in undefined operation. after power is applied to v dd and v dd q (simultaneously) and the cloc k is stable (stable clock is defined as a signal cycling wi thin timing constraints specified for the clock pin), the sdram requires a 100s delay prior to is suing any command other than a command inhibit or nop. starting at some point during this 100s period and continuing at least through the end of this period, comman d inhibit or nop commands must be applied. after the 100s delay has been satisfied wi th at least one command inhibit or nop command having been applied, a precharge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, at least two auto re fresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register program- ming. because the mode register will power up in an unknown state, it must be loaded prior to applying any operational command. if desired, the two auto refresh commands can be issued after the load mode register (lmr) command. the recommended power-up sequence for sdrams: 1. simultaneously apply power to v dd and v dd q. 2. assert and hold cke at a lvttl logic low. 3. provide stable clock signal. stable clock is defined as a signal cycling within timing constraints specified for the clock pin. 4. wait at least 100s prior to issuing any command other than a command inhibit or nop. 5. starting at some point during this 100s period, bring cke high. continuing at least through the end of this period, one or more command inhibit or nop commands must be applied. 6. perform a precharge all command.
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 15 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram register definition 7. wait at least t rp time; during this time, nops or deselect commands must be given. all banks will complete their precharge, thereby placing the device in the all banks idle state. 8. issue an auto refresh command. 9. wait at least t rfc time, during which only nops or command inhibit commands are allowed. 10. issue an auto refresh command. 11. wait at least t rfc time, during which only nops or command inhibit commands are allowed. 12. the sdram is now ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded with desired bit values prior to applying any operational command. using the lmr command, program the mode register. the mode register is progra mmed via the mode register set command with ba1 = 0, ba0 = 0 and retains the stored information until it is programmed again or the device loses power. not programming the mode register upon initialization will result in default settings, which may not be desired. outputs are guaranteed high-z after the lmr command is issued. outputs sh ould be high-z already before the lmr command is issued. 13. wait at least t mrd time, during which only nop or deselect commands are allowed. 14. using the lmr command, program the extended mode register. the low-power extended mode register is programmed via the mode register set command with ba1 = 1, ba0 = 0 and retains the stored information until it is programmed again or the device loses power. not programming the extended mode register upon initializa- tion will result in default settings for the low-power features. the extended mode will default with the temperature sensor enabled, full drive strength, and full array refresh. 15. wait at least t mrd time, during which only nop or deselect commands are allowed. at this point, the dram is ready for any valid command. note: if desired, more than two auto refres h commands can be issued in the sequence. after steps 9 and 10 are complete, repeat them until the desired number of auto refresh + t rfc loops is achieved. register definition mode register to achieve low power consumption, there are two mode registers in the mobile compo- nent: mode register and extended mode register. mode register is discussed in this section. extended mode register is discusse d on page 20. the mode register is used to define the specific mode of operation of th e sdram. this definition includes the selec- tion of bl, a burst type, cl, an operating mode, and a write burst mode, as shown in figure 7 on page 17. the mode register is programmed via the load mode register command and will retain the stored inform ation until it is programmed again or the device loses power. mode register bits m0?m2 specify bl, m3 specifies the type of burst (sequential or inter- leaved), m4?m6 specify cl, m7 and m8 specif y the operating mode, m9 specify the write burst mode (single or programmed burst length), m10 and m11 are reserved and must be set to zero. to address the mode register, m12 and m13 must be set to zero.
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 16 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram register definition the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subs equent operation. violating either of these requirements will result in unspecified operation. burst length (bl) read and write accesses to the sdram are burst oriented, with bl being programmable, as shown in figure 8 on page 19. bl determines the maximum number of column loca- tions that can be accessed for a given read or write command. burst lengths of 1, 2, 4, or 8 locations are available for both the sequ ential and the interleaved burst types, and a full-page burst is available for the sequential mode. the full-page burst is used in conjunction with the burst terminate comma nd to generate arbitrary burst lengths. if a full page burst is not term inated at the end of the page, it could wrap to column zero and continue. reserved states cannot be used because unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to bl is effectively selected. all accesses for that burst take pl ace within this block, meaning that the burst will wrap within the block if a boundary is re ached. the block is uniquely selected by a1? a8 (x16) or a1?a7 (x32) when bl = 2; by a2?a8 (x16) or a2?a7 (x32) when bl = 4; and by a3?a8 (x16) or a3?a7 (x32) when bl = 8. the remaining (least significant) address bit(s) is (are) used to select the starting location wi thin the block. full-page bursts wrap within the page if the boundary is reached. burst type accesses within a given burst may be programme d either to be sequential or interleaved; this is referred to as the burst type and is selected via bit m3. note only a sequential burst is allowed for full page bursts. the ordering of accesses with in a burst is determined by bl, the burst type, and the starting column address, as shown in table 6 on page 18.
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 17 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram register definition figure 7: mode register definition m3 = 0 1 2 4 8 reserved reserved reserved reserved m3 = 1 1 2 4 8 reserved reserved reserved reserved 0 1 burst type sequential interleaved cas latency reserved 1 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 0 1 0 0 mode register (mx) address bus 9 7 6 5 4 3 8 2 1 burst length cas latency bt op mode wb reserved a11 m11 a10 m10 a9 m9 a8 m8 a7 m7 a6 m6 a5 m5 a4 m4 a3 m3 a2 m2 a1 m1 a0 m0 10 11 12 ba0 m12 ba1 m13 mr 13 0 m11 0 ? m10 0 ? m9 valid ? m8 0 ? m7 0 ? m6?m0 valid ? operating mode normal operation all other states reserved mode register definition program mode register program extended mode register m13 m12 0 0 write burst mode programmed burst length single location access m9
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 18 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram register definition note: notes: 1. for full-page accesses: y = 512 (x16), y = 256 (x32). 2. for bl = 2, a1?a8 (x16) or a1 ?a7 (x32) select the block-of-two burst; a0 selects the starting column within the block. 3. for bl = 4, a2?a8 (x16) or a2 ?a7 (x32) select the block-of-f our burst; a0?a1 select the start- ing column within the block. 4. for bl = 8, a3?a8 (x16) or a3?a7 (x32) select the block-of-eight burst; a0?a2 select the starting column wi thin the block. 5. for a full-page burst, the full row is selected, and a0?a8 (x16) or a0?a7 (x32) select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for bl = 1, a0?a8 (x16) or a0?a7 (x32) select the unique column to be accessed, and mode register bit m3 is ignored. cas latency (cl) cl is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data . the latency can be set to 1, 2, or 3 clocks. if a read command is registered at clock edge n and the latency is m clocks, the data will be available by clock edge n + m . the dq will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access time s are met, if a read command is registered at t0 and the table 6: burst definition burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a0?a8 for x16, a0? a7 for x32 (location 0?y) cn, cn + 1, cn + 2, cn + 3, cn + 4..., ?cn - 1, cn? not supported
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 19 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram register definition latency is programmed to 2 clocks, the dq will start driving after t1, and the data will be valid by t2, as shown in figure 8. table 7 indicates the operating frequencies at which each cl setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 8: cas latency write burst mode when m9 = 0, bl programmed into m0?m2 a pplies to both read and write burst. if m9 = 1, all write bursts will only be single lo cation access regardless of the bl setting in the mode register. read burst lengths are unaffected by the state of m9. table 7: cas latency speed allowable operating frequency (mhz) cl = 1 cl = 2 cl = 3 -75m ? 100 133 -8 50 100 125 -10 40 83 100 clk dq t2 t1 t3 t0 cl = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t0 cl = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cl = 2 lz d out t oh t command nop read t ac nop
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 20 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram register definition operating mode the normal operating mode is selected by setting m7, m8, m10, and m11 to zero; all the other combinations of values for m7, m8, m 10, and m11 are reserved for future use and/ or test modes. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. extended mode register the extended mode register controls the func tions beyond those controlled by the mode register. these additional functions are special features of the mobile device. they include tcsr and pasr. figure 9: extended mode register notes: 1. m13 and m12 (ba1 and ba0) must be ?1, 0? to select the extended mode register (vs. the base mode register). 2. rfu: reserved for future use. the extended mode register is programmed via the mode register set command (ba1 = 1, ba0 = 0) and retains the stored in formation until it is programmed again or the device loses power. the extended mode register must be progra mmed with e5 through e11 set to ?0.? the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subse- quent operation. violating either of these re quirements results in unspecified operation. the extended mode register must be programmed to ensure proper operation. temperature-compensate d self refresh (tcsr) tcsr allows the controller to program the refresh interval during self refresh mode, according to the case temperature of the mobile device. this allows great power savings during self refresh during most operating temperature ranges. only during extreme temperatures would the controller have to sele ct a higher tcsr level that will guarantee data during self refresh. 9 7 6 5 4 3 8 2 1 pa s r t cs r set to ? 0 ? emr e13 e12 a11 e11 a10 e10 a9 e9 a8 e8 a7 e7 a 6 e 6 a5 e5 a4 e4 a3 e3 a2 e2 a1 e1 a0 e0 1 0 11 1 2 1 3 partial-array s elf refre s h coverage fullarray (all banks) half array (ba1 = 0) quarter array (ba1 = ba0 = 0) rfu rfu rfu rfu rfu ba1 ba0 m 1 3 0 0 1 1 mo d e regi s ter definition mode register reserved extended mode registe r resereved m 1 2 0 1 0 1 0 e 11 0 ? e 1 0 0 ? e9 0 ? e 8 0 ? e7 0 ? e4 e3 e2 e 1 e0 valid ? operating mo d e normal operation all other states reserved exten d e d mo d e re g ister (ex) e 6 0 ? e5 0 ? e2 0 0 0 0 1 1 1 1 e1 0 0 1 1 0 0 1 1 e0 0 1 0 1 0 1 0 1 maximum ca s e temp. 85 c 70 c 45 c 15 c e4 1 0 0 1 e3 1 0 1 0
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 21 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram register definition every cell in the dram requires refreshing due to the capacitor losing its charge over time. the refresh rate is depe ndent on temperature. at higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. historically, during self refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range, expected. thus, during ambient temperatures, the power consumed during refresh was unneces- sarily high because the refresh rate was se t to accommodate the higher temperatures. setting e4 and e3 allows the dram to acco mmodate more specific temperature regions during self refresh. there are four temperature settings, which will vary the self refresh current according to the selected temperature. this selectable refresh rate will save power when the dram is operating at normal temperatures. partial-array self refresh (pasr) for further power savings during self refresh, the pasr feature allows the controller to select the amount of memory that will be refreshed during self refresh. the refresh options are all banks (banks 0, 1, 2, and 3); two banks (banks 0 and 1); and one bank (bank 0). write and read commands occur to any bank selected during standard operation, but only the selected banks in pasr will be refreshed during self refresh. it?s important to note that data in banks 2 and 3 will be lost when the two-bank option is used. data will be lost in banks 1, 2, and 3 when the one-bank option is used.
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 22 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram register definition commands table 8 provides a quick reference of availabl e commands. this is followed by a written description of each command. three additional truth tables appear following the oper- ation section; these tables provide current state/next state information. notes: 1. cke is high for all comma nds shown except self refresh. 2. a0?a11 provide row address, and ba0, ba 1 determine which bank is made active. 3. a0?a8 (x16) or a0?a7 (x32) provide column address; a10 high enable s the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature; ba0, ba1 determine which bank is bein g read from or written to. 4. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks precharged and ba0, ba1 are ?don?t care.? 5. this command is auto refresh if cke is high, self refresh if cke is low. 6. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 7. a0?a10 define the op-code written to the mode register. ba0?ba1 either select mode regis- ter or the extended mode register (ba0 = ba1 = 0 select the mode register, ba1 = 1, ba0 = 0 selects the extended mode re gister, all other combinations of ba0-ba1 are reserved). 8. activates or deactivates the dq during writes (0-clock delay) and reads (2-clock delay). for x16, ldqm controls dq0?dq7, and udqm cont rols dq8?dq15. for x32, dqm0 controls dq0?dq7, dqm1 controls dq8?dq15, dqm2 co ntrols dq16?23, and dqm3 controls dq24? dq31. command inhibit the command inhibit function prevents new commands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effectively dese- lected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to instruct the selected sdram to perform a nop (ras#, cas#, and we# are high, and cs# is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. table 8: truth table ? commands and dqm operation note 1 applies to entire table name (function) cs# ras# cas# we# dqm addr dq notes command inhibit (nop) hxxxx x x no operation (nop) lhhhx x x active (select bank and activate row) l l h h x bank/row x 2 read (select bank and column, and start read burst) l h l h l/h 8 bank/col x 3 write (select bank and column, and start write burst) l h l l l/h 8 bank/col valid 3 burst terminate lhh l x x active precharge (deactivate row in bank or banks) l l h l x code x 4 auto refresh or self refresh (enter self refresh mode) ll lhx x x 5, 6 load mode register llllxop-codex 7 write enable/output enable ????l ? active8 write inhibit/output high-z ????h ? high-z8
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 23 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram register definition load mode register the mode register is loaded via inputs a0?a11. refer to ?mode register definition? on page 17. the load mode register an d load extended mode register commands can only be issued when all ba nks are idle, and a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a8 (x16) or a0?a7 (x32) selects the starting column lo cation. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. read da ta appears on the dq subject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the corresponding dq will be high-z two clocks later; if the dqm signal was registered low, the dq will provide valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a8 (x16) or a0?a7 (x32) selects the starting column location. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dq is written to the memory array subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be exec uted to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? after a bank has been precharged, it is in the idle state and must be acti- vated prior to any read or write commands being issued to that bank. auto precharge auto precharge is a feature that performs the same individual-bank precharge function described above, without requiring an explic it command. this is accomplished by using a10 to enable auto precharge in conjunctio n with a specific read or write command. a precharge of the bank/row that is addr essed with the read or write command is
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 24 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram register definition automatically performed upon completion of the read or write burst, except in the full-page burst mode where auto precharge does not apply. auto precharge is nonpersis- tent in that it is either enabled or disabl ed for each individual read or write command. auto precharge ensures that the precharge is in itiated at the earliest valid stage within a burst. the user must not issue another comma nd to the same bank until the precharge time ( t rp) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as desc ribed for each burst type in ?operation? on page 25. burst terminate the burst terminate command is used to truncate either fixed-length or full-page bursts. the most recently registered read or write command prior to the burst terminate command will be truncated, as sh own in the operation section of this data sheet. the burst terminate command does not precharge the row; the row will remain open until a precharge command is issued. auto refresh auto refresh is used during normal operation of the sdram and is analogous to cas#-before-ras# (cbr) refresh in conventional drams. this command is nonper- sistent, so it must be issued each time a refresh is required. all active banks must be precharged prior to issuing an auto refresh command. the auto refresh command should not be issued until the minimum t rp has been met after the precharge command as shown in the operation section. the addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the 128mb sdram requires 4,096 auto refresh cycles every 64ms ( t ref), regardless of width option. providing a distributed auto refresh command every 15.6 25s will meet the refresh requirement and ensure that each row is refreshed. alternatively, 4,096 auto refresh commands can be issued in a burst at the minimum cycle rate ( t rfc), once every 64ms. self refresh the self refresh command can be used to reta in data in the sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). after the self refresh command is registered, all the inputs to the sdram become ?don?t care? with the exception of cke, which must remain low. after self refresh mode is engaged, the sdram provides its own internal clocking, causing it to perform its own auto refresh cy cles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indefinite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (stable clock is defi ned as a signal cycling within timing constraints specified for the clock pin) prior to cke going back high. after cke is high, the sdram must have nop commands issued (a minimum of 2 cl ocks, regardless of clock frequency) for t xsr because time is required for the completion of any internal refresh in progress. upon exiting the self refresh mode, auto refresh commands must be issued every 15.625s or less because both self refr esh and auto refresh utilize the row refresh counter.
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 25 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram register definition operation bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be ?opened.? this is accomplished via the active command, which selects both the bank and the row to be activated (see figure 10). after opening a row (issuing an active co mmand), a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks, rounded to 3. this is reflected in figure 11 on page 26, which covers any case where 2 < t rcd (min)/ t ck 3. (the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active comma nds to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active co mmands to different banks is defined by t rrd. figure 10: activating a specific row in a specific bank cs# we# cas# ras# cke clk a0?a10, a11 row address don?t care high ba0, ba1 bank address
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 26 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads figure 11: example: meeting t rcd (min) when 2 < t rcd (min)/ t ck< 3 reads read bursts are initiated with a read command, as shown in figure 12. the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out elem ent from the starting column address will be available following cl after the read command. each subseque nt data-out element will be valid by the next positive clock edge. figure 13 on page 27 shows general timing for each possible cl setting. figure 12: read command clk t2 t1 t3 t0 t command nop active read or write t4 nop rcd don?t care don?t care cs# we# cas# ras# cke clk column address x16: a0?a8 x32: a0?a7 a10 ba0,ba1 high enable auto precharge disable auto precharge bank address a9, a11
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 27 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads upon completion of a burst, assuming no ot her commands have been initiated, the dq will go high-z. a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) data from any read burst may be truncate d with a subsequent read command, and data from a fixed-length read burst may be immediately followed by data from a read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst either follows the last element of a completed burst or the last desired data element of a longer burs t that is being truncated. the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl - 1. figure 13: cas latency this is shown in figure 14 on page 28 fo r cl = 2 and cl = 3; data element n + 3 is either the last of a burst of four or the last desi red of a longer burst. the 128mb sdram uses a pipelined architecture and, therefore, does not require the 2 n rule associated with a prefetch architecture. a read command can be initiated on any clock cycle following a previous read command. full-speed random read accesses can be performed to the same bank, as shown in figure 15 on page 29, or each subsequent read may be performed to a different bank. clk dq t2 t1 t3 t0 cl = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t0 cl = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cl = 2 lz d out t oh t command nop read t ac nop
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 28 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads figure 14: consecutive read bursts notes: 1. each read command may be to either bank. dqm is low. shown with bl = 4. clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 0 cycles cl = 1 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 cycle cl = 2 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read nop t7 x = 2 cycles cl = 3 don?t care transitioning data
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 29 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads figure 15: random read accesses notes: 1. each read command may be to either bank. dqm is low. 2. bl = 1, 2, 4, 8, or full page (if bl > 1, the following read interrupts the previous). data from any read burst may be truncate d with a subsequent write command, and data from a fixed-length read burst may be immediately followed by data from a write command (subject to bus turnaround limitations). the write burst may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that i/o cont ention can be avoided. in a given system design, there may be a possibility that the device driving the input data will go low-z before the sdram dq go high-z. in this case, at least a single-cycle delay should occur between the last read data and the write command. clk dq t2 t1 t4 t3 t6 t5 t0 command address read nop nop bank, col n don?t care d out n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop bank, col n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t0 command address read nop bank, col n d out a d out x d out m read read read bank, col a bank, col x bank, col m cl = 1 cl = 2 cl = 3 transitioning data
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 30 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads figure 16: read-to-write notes: 1. cl = 3 is used for illustration. 2. the read command may be to any bank, an d the write command may be to any bank. 3. if a burst of 1 is used, then dqm is not required. the dqm input is used to avoid i/o contention, as shown in figure 16 and figure 17. the dqm signal must be asserted (high) at least 2 clocks prior to the write command (dqm latency is 2 clocks for output buffers) to suppress data-out from the read. after the write command is registered, the dq will go high-z (or remain high-z), regardless of the state of the dqm signal, provided the dqm was active on the clock just prior to the write command that truncated the read command. if not, the second write will be an invalid write. for example, if dqm was low during t4 in figure 17, then the writes at t5 and t7 would be valid, while the write at t6 would be invalid. the dqm signal must be de-asserted prior to the write command (dqm latency is 0 clocks for input buffers) to ensure that the written data is not masked. figure 16 shows the case where the clock frequency allows for bus contention to be avoided without adding a nop cycle, and figure 17 shows the case where the additional nop is needed. figure 17: read-to-write with extra clock cycle notes: 1. cl = 3 is used for illustration. the re ad command may be to any bank, and the write com- mand may be to any bank. don?t care read nop nop write nop clk t2 t1 t4 t3 t0 dqm dq d out n command d in b address bank, col n bank, col b ds t hz t t ck transitioning data don?t care read nop nop nop nop dqm clk dq d out n t2 t1 t4 t3 t0 command address bank, col n write d in b bank, col b t5 ds t hz t transitioning data
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 31 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads a fixed-length read burst may be followed by, or truncated with, a precharge command to the same bank (provided that au to precharge was not activated), and a full- page burst may be truncated with a precharge command to the same bank. the precharge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl - 1. this is shown in figure 18 on page 32 for each possible cl; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. following the precharg e command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data element(s). in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as desc ribed above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvan- tage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts.
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 32 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads figure 18: read-to-precharge notes: 1. assumes t ras(min) has been satisfied pr ior to the precharge command. 2. n + 3 is either the last data element of a bl = 4 or the last desired data element of a longer burst. 3. dqm is low. full-page read bursts can be truncated with the burst terminate command, and fixed-length read bursts may be truncated with a burst terminate command, provided that auto precharge was not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl - 1. this is shown in figure 19 on page 33 for each possible cl; data element n + 3 is the last desired data element of a longer burst. clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank a , col n nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 bank a , row bank ( a or all) don?t care x = 0 cycles cl = 1 x = 1 cycle cl = 2 cl = 3 bank a , col n bank a , row bank ( a or all) bank a , col n bank a , row bank ( a or all) x = 2 cycles transitioning data
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 33 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads figure 19: terminating a read burst notes: 1. page remains open a fter a burst terminate command. 2. n + 3 is either the last data element of bl = 4 or the last desired data element of a longer burst. 3. dqm is low. don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop x = 0 cycles cl = 1 x = 1 cycle cl = 2 cl = 3 x = 2 cycles transitioning data
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 34 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads writes write bursts are initiated with a write command, as shown in figure 20. the starting column and bank addresses ar e provided with the write command, and auto precharge either is enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at th e completion of the burst. for the write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dq will remain high-z, and any additional input data will be ignored (see figure 21 on page 35). a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) figure 20: write command data for any write burst may be truncate d with a subsequent write command, and data for a fixed-length write burst may be immediately followed by data for a write command. the new write command can be issued on any clock following the previous write command, and the data provided coin cident with the new command applies to the new command. an example is shown in figure 21 on page 35. data n + 1 is either the last of a burst of two or the last desired of a longer burst. the 128mb sdram uses a pipe- lined architecture and, therefore, does not require the 2n rule associated with a prefetch architecture. a write command can be initiated on any clock cycle following a previous write command. full-speed random write acce sses within a page can be performed to the same bank, as shown in figure 22 on page 35, or each subsequent write may be performed to a different bank. cs# we# cas# ras# cke clk column address don?t care high enable auto precharge disable auto precharge bank address x16: a0?a8 x32: a0?a7 a10 ba0,1 a9, a11 valid address
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 35 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads figure 21: write burst notes: 1. bl = 2. dqm is low. figure 22: write-to-write notes: 1. dqm is low. each wri te command may be to any bank. data for any write burst may be truncate d with a subsequent read command, and data for a fixed-length write burst may be immediately followed by a read command. after the read command is registered, the data inputs will be ignored, and writes will not be executed. an example is shown in figure 24 on page 36. data n + 1 is either the last of a burst of two or the last desired of a longer burst. data for a fixed-length write burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not acti- vated), and a full-page write burst may be truncated with a precharge command to the same bank. the precharge command should be issued t wr after the clock edge at which the last desired input data element is registered. the auto precharge mode requires a t wr of at least one clock plus time, regardless of frequency. in addition, when truncating a write burst, the dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge command. an example is shown in figure 25 on page 37. data n + 1 is either the last of a burst of two or the la st desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. the precharge can be issued coincident with the second clock (see figure 25 on page 37). clk dq d in n t2 t1 t3 t0 command address nop nop write d in n + 1 nop bank, col n don?t care transitioning data don?t care clk dq t2 t1 t0 command address nop write write bank, col n bank, col b d in n d in n + 1 d in b transitioning data
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 36 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as desc ribed above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvan- tage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. figure 23: random write cycles notes: 1. each write command may be to any bank. 2. dqm is low. 3. example shows bl = 1 or an interrupting bl > 1. figure 24: write-to-read notes: 1. the write command may be to any bank , and the read command may be to any bank. 2. dqm is low. 3. cl = 2 for illustration. 4. data n + 1 is either the last data of bl = 1 or the last desired of a longer burst. don?t care clk dq d in n t2 t1 t3 t0 command address write bank, col n d in a d in x d in m write write write bank, col a bank, col x bank, col m transitioning data don?t care clk dq t2 t1 t3 t0 command address nop write bank, col n d in n d in n + 1 d out b read nop nop bank, col b nop d out b + 1 t4 t5 transitioning data
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 37 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads figure 25: write-to-precharge notes: 1. dqm could remain low in this example if the write burst is a fixed length of two. fixed-length or full-page write bursts can be truncated with the burst terminate command. when truncating a write burst, the input data applied coincident with the burst terminate command will be ignored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate command. this is shown in figure 26, where data n is the last desired data element of a longer burst. figure 26: terminating a write burst notes: 1. dqms are low. dqm clk dq t2 t1 t4 t3 t0 command address bank a , col n t5 nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row dqm dq command address bank a , col n nop write precharge nop nop d in n d in n + 1 active t rp don?t care bank ( a or all) t wr bank a , row t6 nop nop t wr@ t ck 15ns t wr@ t ck < 15ns transitioning data clk dq t2 t1 t0 command address bank, col n write burst terminate next command d in n (address) (data) transitioning data don?t care
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 38 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads figure 27: precharge command precharge the precharge command (see figure 27) is used to deactivate the open row in a particular bank or the open row in all bank s. the bank(s) will be available for a subse- quent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 ar e treated as ?don?t care.? after a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. power-down power-down occurs if cke is registered low coincident with a nop or command inhibit when no accesses are in progress. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and outp ut buffers, excluding cke, for maximum power savings while in standby. the device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. the power-down state is exited by regi stering a nop or command inhibit and cke high at the desired clock edge (meeting t cks). see figure 28 on page 39. cs# we# cas# ras# cke clk a10 don?t care high all banks bank selected a0-a9 ba0, ba1 bank address valid address
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 39 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads figure 28: power-down clock suspend the clock suspend mode occurs when a column access/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deactivated, ?freezing? the synchronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the dq pins remains driven; and burst counters are not incremented as long as the clock is suspended. (see examples in figure 29 and in figure 30 on page 40.) figure 29: clock suspend during write burst notes: 1. for this example, burst leng th = 4 or greater, and dm is low. clock suspend mode is exited by registering cke high; the internal clock and related operation will resume on the subsequent positive clock edge. don?t care t ras t rcd t rc all banks idle input buffers gated off exit power-down mode. ( ) ( ) ( ) ( ) ( ) ( ) t cks > t cks command nop active enter power-down mode. nop clk cke ( ) ( ) ( ) ( ) don?t care d in command address write bank, col n d in n nop nop clk t2 t1 t4 t3 t5 t0 cke internal clock nop d in n + 1 d in n + 2 transitioning data
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 40 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads burst read/single write the burst read/single write mode is entere d by programming the write burst mode bit (m9) in the mode register to a logic 1. in this mode, all write commands result in the access of a single column location (burst of 1), regardless of the programmed burst length. read commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (m9 = 0). figure 30: clock suspend during read burst notes: 1. for this example, cl = 2, bl = 4 or greater, and dqm is low. concurrent auto precharge an access command (read or write) to an other bank while an access command with auto precharge enabled is executing is not allowed by sdrams, unless the sdram supports concurrent auto precharge. mi cron sdrams support concurrent auto precharge. four cases where concurrent auto precharge occurs are defined below. read with auto precharge ? interrupted by a read (with or with out auto precharge): a read to bank m will inter- rupt a read on bank n , cl later. the precharge to bank n will begin when the read to bank m is registered (figure 31 on page 41). ? interrupted by a write (with or with out auto precharge): a write to bank m will interrupt a read on bank n when registered. dqm should be used 2 clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 32 on page 41). don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 cke internal clock nop transitioning data
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 41 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads figure 31: read with auto precharge interrupted by a read notes: 1. dqm is low, bl = 4 or greater, and cl = 3. figure 32: read with auto precharge interrupted by a write notes: 1. dqm is high at t2 to prevent d out a + 1 from contending with d in d at t4. write with auto precharge ? interrupted by a read (with or with out auto precharge): a read to bank m will inter- rupt a write on bank n when registered, with the data -out appearing cl later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered 1 clock prior to the read to bank m (figure 33 on page 42). don?t care clk dq d out a t2 t1 t4 t3 t6 t5 t0 command read - ap bank n nop nop nop nop d out a + 1 d out d d out d + 1 nop t7 bank n cl = 3 (bank m ) bank m address idle nop bank n , col a bank m , col d read - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active read with burst of 4 precharge rp - bank n t rp - bank m cl = 3 (bank n ) transitioning data clk dq d out a t2 t1 t4 t3 t6 t5 t0 command nop nop nop nop d in d d in d + 2 d in d + 3 nop t7 bank n bank m address idle nop dqm bank n , col a bank m , col d write - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active write with burst of 4 write-back rp - bank n t wr - bank m cas latency = 3 (bank n ) read - ap bank n 1 don?t care transitioning data d in d + 1
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 42 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads ? interrupted by a write (with or with out auto precharge): a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid data write to bank n will be data registered 1 clock prior to a write to bank m (figure 34). figure 33: write with auto precharge interrupted by a read notes: 1. dqm is low. figure 34: write with auto pr echarge interrupted by a write notes: 1. dqm is low. don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in a + 1 d in a nop nop t7 bank n bank m address bank n , col a bank m , col d read - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active read with burst of 4 t t rp - bank m d out d d out d + 1 cl = 3 (bank m ) rp - bank n wr - bank n transitioning data don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in d + 1 d in d d in a + 1 d in a + 2 d in a d in d + 2 d in d + 3 nop t7 bank n bank m address nop bank n , col a bank m , col d write - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active write with burst of 4 write-back wr - bank n t rp - bank n t wr - bank m transitioning data
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 43 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads notes: 1. cke n is the logic state of cke at clock edge n ; cke n - 1 was the state of cke at the previous clock edge. 2. current state is the state of the sd ram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of com- mand n . 4. all states and sequences not sh own are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that t cks is met). 6. exiting self refresh at clock edge n will put the device in the all banks idle state after t xsr is met. command inhibit or nop co mmands should be issued on any clock edges occurring during the t xsr period. a minimum of two nop commands must be provided during t xsr period. 7. after exiting clock suspend at clock edge n , the device will resume operation and recognize the next command at clock edge n + 1. table 9: truth table ? cke notes 1?4 apply to entire table cke n - 1 cke n current state comand n action notes l l power-down x maintain power-down self refresh x maintain self refresh clock suspend x mainta in clock suspend l h power-down command inhibit or nop exit power-down 5 self refresh command inhibit or nop exit self refresh 6 clock suspend x exit clock suspend 7 h l all banks idle command inhibi t or nop power-down entry all banks idle auto refresh self refresh entry reading or writing write or nop clock suspend entry h h see table 10 on page 44
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 44 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads notes: 1. this table applies when cke n - 1 was high and cke n is high (see table 9 on page 43) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where note d; that is, the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: 4. the following states must not be interrupted by a command issued to the same bank. com- mand inhibit or nop commands or allowabl e commands to the other bank should be issued on any clock edge occurring during th ese states. allowable commands to the other bank are determined by its current state and table 10 and according to table 11 on page 46. table 10: truth table ? current state bank n , command to bank n notes 1?6 apply to entire tabl e; notes appear below table current state cs# ras# cas# we# command (action) notes any hxxx command inhibit (nop/continue previous operation) l hhh no operation (nop/continue previous operation) idle l l h h active (select an d activate row) lllh auto refresh 7 llll load mode register 7 llhl precharge 11 row activelhlh read (select column and start read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (deactivate ro w in bank or banks) 8 read (auto precharge disabled) lhlh read (select column and start new read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (truncate read burst, start precharge) 8 lhhl burst terminate 9 write (auto precharge disabled) lhlh read (select column and start read burst) 10 lhl l write (select column an d start new write burst) 10 llhl precharge (truncate write burst, start precharge) 8 lhhl burst terminate 9 idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, wi th auto precharge disabled, and has not yet terminated or been terminated. precharging: starts with registration of a precharge command and ends when t rp is met. after t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. after t rcd is met, the bank will be in the row active state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a wr ite command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state.
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 45 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads 5. the following states must not be inte rrupted by any executable command; command inhibit or nop commands must be applied on ea ch positive clock edge during these states. refreshing starts with registration of an auto refresh command and ends when t rfc is met. after t rfc is met, the sdram will be in the all banks idle state. 6. all states and sequences not sh own are illegal or reserved. 7. not bank-specific; require s that all banks are idle. 8. may or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. not bank-specific; burst terminate affects th e most recent read or write burst, regard- less of bank. 10. reads or writes listed in the command (act ion) column include reads or writes with auto precharge enabled and reads or wr ites with auto precharge disabled. 11. does not affect the state of the ba nk and acts as a nop to that bank. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. after t mrd is met, the sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. after t rp is met, all banks will be in the idle state.
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 46 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads notes: 1. this table applies when cke n - 1 was high and cke n is high (see table 9 on page 43) and after t xsr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted; that is, the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given comma nd is allowable). exceptions are covered in the notes below. 3. current state definitions: 4. auto refresh, self refresh, and load mo de register commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. table 11: truth table ? current state bank n , command to bank m notes 1?6 apply to entire table; notes appear below and on next page current state cs# ras# cas# we# command (action) notes any hxxx command inhibit (n op/continue previous operation) l hhh no operation (nop/conti nue previous operation) idle xxxx any command otherwise allowed to bank m row activating, active, or precharging llhh active (select an d activate row) lhlh read (select column and start read burst) 7 lhl l write (select column and start write burst) 7 llhl precharge read (auto precharge disabled) llhh active (select an d activate row) lhlh read (select column and start new read burst) 7, 10 lhl l write (select column and start write burst) 7, 11 llhl precharge 9 write (auto precharge disabled) llhh active (select an d activate row) lhlh read (select column and start read burst) 7, 12 lhl l write (select column an d start new write burst) 7, 13 llhl precharge 9 read (with auto precharge) llhh active (select an d activate row) lhlh read (select column and start new read burst) 7, 8, 14 lhl l write (select column and start write burst) 7, 8, 15 llhl precharge 9 write (with auto precharge) llhh active (select an d activate row) lhlh read (select column and start read burst) 7, 8, 16 lhl l write (select column an d start new write burst) 7, 8, 17 llhl precharge 9 idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regi ster accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, wi th auto precharge disabled, and has not yet terminated or been terminated. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a wr ite command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state.
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 47 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram reads 6. all states and sequences not sh own are illegal or reserved. 7. reads or writes to bank m listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. concurrent auto precharge: bank n will initiate the auto precharge command when its burst has been interrupted by bank m ?s burst. 9. burst in bank n continues as initiated. 10. for a read without auto precharge interrup ted by a read (with or without auto pre- charge), the read to bank m will interrupt the read on bank n , cl later (see figure 14 on page 28). 11. for a read without auto precharge interrup ted by a write (with or without auto pre- charge), the write to bank m will interrupt the read on bank n when registered (see figure 16 and figure 17 on page 30). dqm should be used on e clock prior to the write command to preven t bus contention. 12. for a write without auto precharge interru pted by a read (with or without auto pre- charge), the read to bank m will interrupt the write on bank n when registered (see figure 24 on page 36) with the data-out appearin g cl later. the last valid write to bank n will be data-in registered 1 cl ock prior to the read to bank m . 13. for a write without auto precharge interrupt ed by a write (with or without auto pre- charge), the write to bank wi ll interrupt the write on bank n when registered (see figure 22 on page 35). the last valid write to bank n will be data-in registered 1 clock prior to the read to bank m . 14. for a read with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n , cl later. the precharge to bank n will begin when the read to bank m is registered (see figure 31 on page 41). 15. for a read with auto precharge interrupted by a write (with or with out auto precharge), the write to bank m will interrupt the read on bank n when registered . dqm should be used 2 clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (see figure 32 on page 41). 16. for a write with auto precha rge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cl later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the la st valid write bank n will be data-in registered 1 clock prior to the read to bank m (see figure 33 on page 42). 17. for a write with auto precha rge interrupted by a write (wit h or without auto precharge), the write to bank m will interrupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when th e write to bank m is reg- istered. the last va lid write to bank n will be data registered 1 clock to the write to bank m (see figure 34 on page 42).
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 48 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram electrical specifications electrical specifications stresses greater than those listed in table 12 may cause permanent damage to the device. this is a stress rating only, and functi onal operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to abso lute maximum rating conditio ns for extended periods may affect reliability. temperature and thermal impedance it is imperative that the mobile sdram device?s temperature specifications, shown in table 13 on page 49, be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specificat ions. an important step in maintaining the proper junction temperature is using the device?s thermal impedances correctly. the thermal impedances are listed in table 14 on page 49 for the applicable die revision and packages being made available. these thermal impedance values vary according to the density, package, and particular design used for each device. incorrectly using thermal impedances can produce significant errors. read micron tech- nical note tn-00-08, ?thermal applications ? prior to using the thermal impedances listed in table 14 on page 49. to ensure the co mpatibility of current and future designs, contact micron applications engineerin g to confirm thermal impedance values. the sdram device?s safe junction temperature range can be maintained when the t c specification is not exceeded. in applications where the device?s ambient temperature is too high, use of forced air and/or heat sinks may be required to satisfy the case tempera- ture specifications. table 12: absolute maximum ratings parameter min max rating voltage on v dd /v dd q supply relative to v ss (lc devices) ?1 +4.6 v relative to v ss (v devices) 0.5 +3.6 v voltage on inputs, nc or i/o pins relative to v ss (lc devices) ?1 +4.6 v relative to v ss (v devices) ?0.5 +3.6 v operating temperature t a (commercial) t a (industrial) t a (extended) 0 ?40 ?25 +70 +85 +75 c storage temperature (plastic) ?55 +150 c
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 49 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram electrical specifications notes: 1. max operating case temperature, t c , is measured in the center of the package on the top side of the device, as shown in figures 35, 36, and 37 on page 50. 2. device functionality is not guarant eed if the device exceeds maximum t c during operation. 3. all temperature specific ations must be satisfied. 4. the case temperature should be measured by gluing a thermocouple to the top center of the component. this shou ld be done with a 1mm bead of conductive epoxy, as defined by the jedec eia/jesd51 standards. care should be taken to ensure the thermocouple bead is touching the case. 5. operating ambient temperatur e surrounding the package. notes: 1. for designs expected to last beyond the die revision listed, contact micron applications engineering to confirm thermal impedance values. 2. thermal resistance data is sampled from mult iple lots, and the values should be viewed as typical. 3. these are estimates; actual results may vary. 4. thermal impedance values were obtained using the 128mb sdram 54-pin tsop. ta bl e 1 3 : te mp er a t ure l im it s parameter symbol min max units notes operating case temperature: commercial industrial t c 0 ?40 80 90 c 1, 2, 3, 4 junction temperature: commercial industrial t j 0 ?40 85 95 c 3 ambient temperature: commercial industrial t a 0 ?40 70 85 c 3, 5 peak reflow temperature t peak ?260c table 14: thermal impedance simulated values die revision package substrate ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) g 54-pin tsop 4 2-layer 86.2 67.8 62 46.9 11.3 4-layer 58.9 50.7 47.6 41.5 54-ball vfbga 2-layer 72.1 57.3 50.6 36.0 4.1 4-layer 54.5 46.6 42.8 35.5 90-ball vfbga 2-layer 64.6 50.8 45.3 37.5 1.8 4-layer 48.2 41.1 38.1 32.1
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 50 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram electrical specifications figure 35: example temperature test point location, 54-pin tsop: top view figure 36: example temperature test point location, 54-ball vfbga: top view figure 37: example temperature test point location, 90-ball vfbga: top view 22.22mm 11.11mm test point 10.1 6 mm 5.08mm 8.00mm 4.00mm test point 4.00mm 8.00mm test point 6 .50mm 13.00mm 4.00mm 8.00mm
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 51 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram electrical specifications table 15: dc electrical characteristics and operating conditions (lc version) notes 1, 6 apply to entire tabl e; notes appear on page 56; v dd = +3.3v 0.3v, v dd q = +3.3v 0.3v parameter/condition symbol min max units notes supply voltage v dd 33.6v i/o supply voltage v dd q3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 22 input low voltage: logic 0; all inputs v il ?0.3 0.8 v 22 data output high voltage: logic 1; all inputs v oh 2.4 ? v data output low voltage: logic 0; all inputs v ol ?0.4v input leakage current: any input 0v v in v dd (all other pins not under test = 0v) i i ?5 5 a output leakage current: dq are disabled; 0v v out v dd q i oz ?5 5 a table 16: dc electrical characteristics and operating conditions (v version) notes 1, 6 apply to entire tabl e; notes appear on page 56; v dd = 2.5 0.2v, v dd q = +2.5v 0.2v or +1.8v 0.15v parameter/condition symbol min max units notes supply voltage v dd 2.3 2.7 v i/o supply voltage v dd q1.65 2.7 v input high voltage: logic 1; all inputs v ih (dq) 1.25 v dd q + 0.3 v 22 v ih (non-dq) 1.25 v dd + 0.3 input low voltage: logic 0; all inputs v il ?0.3 +0.55 v 22 data output high voltage: logic 1; all inputs v oh v dd q - 0.2 ? v data output low voltage: logic 0; all inputs v ol ?0.2v input leakage current: any input 0v v in v dd (all other pins not under test = 0v) i i ?5 5 a output leakage current: dq are disabled; 0v v out v dd q i oz ?5 5 a
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 52 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram electrical specifications table 17: electrical characteristics and recommended ac operating conditions notes 5, 6, 7, 8, 9, 11 apply to en tire table; notes appear on page 56 ac characteristics symbol -75m -8 -10 units notes parameter min max min max min max access time from clk (positive edge) cl = 3 t ac (3) ? 5.4 ? 7 ? 7 ns cl = 2 t ac (2)?6?8?8ns cl = 1 t ac (1) ? na ? 19 ? 22 ns address hold time t ah0.8?1?1?ns address setup time t as 1.5 ? 2.5 ? 2.5 ? ns clk high-level width t ch3?3?3?ns clk low-level width t cl2.5?3?3?ns clock cycle time cl = 3 t ck (3) 7.5 ? 8 ? 10 ? ns 23 cl = 2 t ck (2) 9.6 ? 9.6 ? 12 ? ns 23 cl = 1 t ck (1) n/a ? 20 ? 25 ? ns 23 cke hold time t ckh1?1?1?ns cke setup time t cks 2.5 ? 2.5 ? 2.5 ? ns cs#, ras#, cas#, we#, dqm hold time t cmh0.8?1?1?ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 ? 2.5 ? 2.5 ? ns data-in hold time t dh0.8?1?1?ns data-in setup time t ds 1.5 ? 2.5 ? 2.5 ? ns data-out high-z time cl = 3 t hz (3) ? 5.4 ? 7 ? 7 ns 10 cl = 2 t hz (2)?6?8?8ns10 cl = 1 t hz (1) ? na ? 19 ? 22 ns 10 data-out low-z time t lz1?1?1?ns data-out hold time (load) t oh 2.5 ? 2.5 ? 2.5 ? ns 27 data-out hold time (no load) t oh n 1.8 ? 1.8 ? 1.8 ? ns active-to-precharge command t ras 44 120,000 48 120,000 50 120,000 ns active-to-active command period t rc 66 ? 80 ? 100 ? ns active-to-read or write delay t rcd19?20?20?ns refresh period (4,096 rows) t ref ? 64 ? 64 ? 64 ms auto refresh command period t rfc 66 ? 80 ? 100 ? ns precharge command period t rp 19 ? 20 ? 20 ? ns active bank a to active bank b command t rrd2?2?2? t ck transition time t t 0.3 1.2 0.5 1.2 0.5 1.2 ns 7 write recovery time auto precharge mode (a) manual precharge mode (m) t wr (a) 1 clk +7.5ns ?1 clk +7ns ?1 clk +5ns ??24 t wr (m)15?15?15?ns25 exit self refresh to active command t xsr 67 ? 80 ? 100 ? ns 20
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 53 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram electrical specifications table 18: ac functional characteristics notes 5, 6, 7, 8, 9, 11 apply to en tire table; notes appear on page 56 parameter symbol -75m -8 -10 units notes read/write command to read/write command t ccd111 t ck 17 cke to clock disable or power-down entry mode t cked111 t ck 14 cke to clock enable or power-down exit setup mode t ped 1 1 1 t ck 14 dqm to input data delay t dqd000 t ck 17 dqm to data mask during writes t dqm000 t ck 17 dqm to data high-z during reads t dqz222 t ck 17 write command to input data delay t dwd000 t ck 17 data-in to active command t dal 5 5 5 t ck 15, 21 data-in to precharge command t dpl222 t ck 16, 21 last data-in to burst stop command t bdl111 t ck 17 last data-in to ne w read/write command t cdl111 t ck 17 last data-in to precharge command t rdl222 t ck 16, 21 load mode register command to active or refresh command t mrd222 t ck 26 data-out to high-z from precharge command cl = 3 t roh(3)333 t ck 17 cl = 2 t roh(2)222 t ck 17 cl = 1 t roh(1) 1 1 t ck 17
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 54 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram electrical specifications table 19: i dd specifications and conditions (x16) notes 1, 3, 6, 11, 13, 31 apply to en tire table; notes appear on page 56; v dd = v dd q = +3.3v 0.3v or v dd = v dd q = 2.5v 0.2v or v dd = +2.5v 0.2v, v dd q = +1.8v 0.15v parameter/condition symbol max units notes -75m -8 -10 operating current: active mode ; burst = 2; read or write; t rc = t rc (min) i dd1 130 130 100 ma 18, 19 standby current: power-down mode; all banks idle; cke = low i dd2 450 450 450 a 12, 33 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd3 40 40 35 ma 19 operating current: burst mode; page burst; read or write; all banks active i dd4 115 100 95 ma 18, 19 auto refresh current: cke = high; cs# = high t rfc = t rfc (min) i dd5 225 210 170 ma 12, 18, 19, 32, 33 t rfc = 15.625s i dd6 333ma table 20: i dd 7 self refresh current options (x16) note 4 applies to entire table; note appears on page 56; v dd = v dd q = +3.3v 0.3v or v dd = v dd q = 2.5v 0.2v or v dd = +2.5v 0.2v, v dd q = +1.8v 0.15v temperature-compensated self refresh (tcsr) parameter/condition max temperature -75m/-8/-10 units self refresh current: cke < 0.2v (e4 = 1, e3 = 1) 85oc 800 a self refresh current: cke < 0.2v (e4 = 0, e3 = 0) 70oc 500 a self refresh current: cke < 0.2v (e4 = 0, e3 = 1) 45oc 350 a self refresh current: cke < 0.2v (e4 = 1, e3 = 0) 15oc 300 a
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 55 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram electrical specifications table 21: i dd specifications and conditions (x32) notes 1, 3, 6, 11, 13, 31 apply to en tire table; notes appear on page 56; v dd = v dd q = +3.3v 0.3v or v dd = v dd q = 2.5v 0.2v or v dd = +2.5v 0.2v, v dd q = +1.8v 0.15v parameter/condition symbol max units notes -75m -8 -10 operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd1 150 150 120 ma 18, 19 standby current: power-down mode; all banks idle; cke = low i dd2 450 450 450 a 12, 33 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd3 45 45 40 ma 19 operating current: burst mode; page burst; read or write; all banks active i dd4 130 115 110 ma 18, 19 auto refresh current: cke = high; cs# = high t rfc = t rfc (min) i dd5 235 220 180 ma 12, 18, 19, 32, 33 t rfc = 15.625s i dd6 333ma table 22: i dd 7 self refresh current options (x32) note 4 applies to entire table; notes appear on page 56; v dd = v dd q = +3.3v 0.3v or v dd = v dd q = 2.5v 0.2v or v dd = +2.5v 0.2v, v dd q = +1.8v 0.15v temperature-compensated self refresh (tcsr) parameter/condition max temperature -75m/-8/-10 units self refresh current: cke < 0.2v (e4 = 1, e3 = 1) 85oc 1000 a self refresh current: cke < 0.2v (e4 = 0, e3 = 0) 70oc 550 a self refresh current: cke < 0.2v (e4 = 0, e3 = 1) 45oc 400 a self refresh current: cke < 0.2v (e4 = 1, e3 = 0) 15oc 350 a table 23: capacitance (fbga pacakge) note 2 applies to entire table; notes appear on page 56 parameter symbol min max units notes input capacitance: clk c i1 1.5 3.5 pf 28 input capacitance: all other input-only pins c i2 1.5 3.8 pf 29 input/output capacitance: dq c io 3.0 6.0 pf 30 table 24: capacitance (tsop pacakge) note 2 applies to entire table; notes appear on page 56 parameter symbol min max units notes input capacitance: clk c i1 2.5 3.5 pf 28 input capacitance: all other input-only pins c i2 2.5 3.8 pf 29 input/output capacitance: dq c io 4.0 6.0 pf 30
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 56 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram notes notes 1. all voltages are referenced to vss. 2. this parameter is sampled. v dd , v dd q = +3.3v; t a = 25c; pin under test biased at 1.4v, f = 1 mhz. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full operationa l temperature range is ensured (t a = commercial, it, or xt). 6. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be pow- ered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh require- ment is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specification, the cl ock and cke must tran- sit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5v (for lc devices) or at 1.25v (v devices) with equivalent load: 10. t hz defines the time at which the output achi eves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests use established values for v il and v ih , with timing referenced to v ih /2 crossover point. if the input transition time is longer than 1ns, then the tim- ing is referenced at v il ( max ) and v ih ( min ) and no longer at the v ih /2 crossover point. established tester values follow: v il = 0v, v ih = 3.0v for lc devices and v ih = 2.3v for v devices. 12. other input signals are allowed to transition no more than once every 2 clocks and are otherwise at valid v ih or v il levels. 13. i dd specifications are tested after th e device is properly initialized. 14. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 18. the i dd current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. address transitions average one transition every 2 clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 125mhz for -8 and t ck = 100mhz for -10. q 30pf
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 57 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram notes 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one-third of the cycle rate. v il undershoot: v il (min) = ?2v for a pulse width 3ns and cannot be greater than one-third of the cycle rate. 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for th e clock pin) during access or precharge states (read, write, including t wr, and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget ( t rp) begins at 5.4ns for -8 after the first clock delay afte r the last write is executed. 25. manual precharge mode only. 26. jedec and pc100 specify 3 clocks. 27. parameter guaranteed by design. 28. pc100 specifies a maximum of 4pf. 29. pc100 specifies a maximum of 5pf. 30. pc100 specifies a maximum of 6.5pf. 31. for -75m, cl = 3 and t ck = 7.5ns; for -8, cl = 3 and t ck = 8ns; for -10, cl = 3 and t ck = 10ns. 32. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 33. specified with i/os in steady state condition.
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 58 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams timing diagrams figure 38: initialize and load mode register notes: 1. the two auto refresh commands at t9 an d t19 may be applied either before load mode register (lmr) command. 2. pre = precharge command, lmr = load mode register co mmand, ar = auto refresh command, act = active command, ra = row address, and ba = bank address. 3. the load mode register both for mode regi ster and for extended mode register, and two auto refresh commands can be in any orde r. however, all must occur prior to an active command. 4. optional re fresh command. 5. although not required, to prev ent bus contention, it is su ggested to keep dqm high dur- ing the initialization sequence. see table 17 on page 52. clk t ck t0 t1 t3 t5 t7 t9 t19 t29 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) cke ba0, ba1 load extended mode register load mode register t cks power-up: v dd and clk stable t = 100s t ckh ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqml, dqmu 5 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq high-z a0?a9, a11 ra a10 ra all banks lmr 3 nop pre lmr 3 ar ar 4 act t cms t cmh ba0 = l, ba1 = h t as t ah t as t ah ba0 = l, ba1 = l ( ) ( ) ( ) ( ) code code t as t ah code code ( ) ( ) ( ) ( ) pre all banks t as t ah ( ) ( ) ( ) ( ) don?t care ba ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp t mrd t mrd t rp t rfc t rfc ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) command 1,2 ( ) ( ) ( ) ( )
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 59 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 39: power-down mode notes: 1. violating refresh requirements during power-down may result in a loss of data. see table 17 on page 52. t ch t cl t ck two clock cycles cke 1 clk dq all banks idle, enter power-down mode precharge all active banks input buffers gated off while in power-down mode exit power-down mode ( ) ( ) don?t care t cks t cks command t cmh t cms precharge nop nop active nop ( ) ( ) ( ) ( ) all banks idle ba0, ba1 bank bank(s) ( ) ( ) ( ) ( ) high-z t ah t as t ckh t cks dqml, dqmu ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a0?a9, a11 row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 tn + 2 ( ) ( )
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 60 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 40: clock suspend mode notes: 1. for this example, bl = 2, cl = 3, and auto precharge is disabled. 2. x16: a9 and a11 = ?don?t care.? x32: a8, a9 and a11 = ?don?t care.? see table 17 on page 52. t ch t cl t ac t lz dqmu, dqml clk a0-a9, a11 2 dq ba0, ba1 a10 t oh d out m t ah t as t ah t as t ah t as bank t dh d in e t ac t hz d out m + 1 command 1 t cmh t cms nop nop nop nop nop read write cke t cks t ckh bank column m t ds d in e + 1 nop t ckh t cks t cmh t cms 2 column e 2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t ck don?t care undefined
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 61 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 41: auto refresh mode notes: 1. each auto refresh command performs a re fresh cycle. back-to-back commands are not required. see table 17 on page 52. 2. t rfc must not be interrupted by any exec utable command; comm and inhibit or nop commands must be applied on each positive clock edge during t rfc. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) all banks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ch t cl t ck cke clk dq t rfc 1, 2 t rp command t cmh t cms nop nop bank active auto refresh nop nop precharge precharge all active banks auto refresh t rfc 1, 2 high-z ba0, ba1 bank(s) ( ) ( ) ( ) ( ) ( ) ( ) t ah t as t ckh t cks nop ( ) ( ) ( ) ( ) ( ) ( ) dqmu, dqml a0?a9, a11 row ( ) ( ) ( ) ( ) single bank a10 row ( ) ( ) t0 t1 t2 tn + 1 to + 1 don?t care ( ) ( ) ( ) ( ) ( ) ( )
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 62 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 42: self refresh mode notes: 1. no maximum time limit for self refresh. t ras (max) only applies to non-self refresh mode. 2. t xsr requires a minimum of 2 clocks regardless of frequency or timing. 3. as a general rule, any time self refresh is ex ited, the dram may not reenter the self refresh mode until all rows have be en refreshed via the auto refr esh command at the distrib- uted refresh rate, ( t ref/number of rows), or faster. ho wever, the following exception is allowed. self refresh mode may be reentered any time after exiting if the following condi- tions are all met: 3a. the dram has been in the self refresh mo de for a minimum of 64ms prior to exiting. 3b. t xsr has not been violated. 3c. at least two auto refresh commands are performed during each 15.625s interval while the dram remains out of the self refresh mode. see table 17 on page 52. don?t care t ch t cl t ck t rp cke clk dq enter self refresh mode precharge all active banks t xsr 2 clk stable prior to exiting self refresh mode exit self refresh mode (restart refresh time base) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) command t cmh t cms auto refresh precharge nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ba0, ba1 bank(s) high-z t cks ah as auto refresh > t ras 1 ( ) ( ) ( ) ( ) t ckh t cks dqmu, dqml ( ) ( ) ( ) ( ) t t a0?a9, a11 ( ) ( ) ( ) ( ) all banks single bank a10 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 to + 1 to + 2 ( ) ( ) ( ) ( )
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 63 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 43: read ? without auto precharge notes: 1. for this example, bl = 4, cl = 2, and the read burst is followed by a ?manual? precharge. 2. x16: a9 and a11 = ?don?t care.? x32: a8, a9, and a11 = ?don?t care.? see table 17 on page 52. all banks t ch t cl t ac t lz t rp t ras t rcd cas latency t rc t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t oh d out m +3 t ac t oh t ac t oh t ac d out m +2 d out m +1 t cmh t cms precharge nop nop nop active nop read nop active disable auto precharge single banks don?t care undefined column m 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 dqmu, dqml cke clk a0?a9, a11 dq ba0, ba1 a10 command t ck
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 64 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 44: read ? with auto precharge notes: 1. for this example, bl = 4 and cl = 2. 2. x16: a9 and a11 = ?don?t care.? x32: a8, a9, and a11 = ?don?t care.? see table 17 on page 52. enable auto precharge t ch t cl t ac t lz t rp t ras t rcd cas latency t rc dqmu, dqml cke clk a0?a9, a11 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank don?t care undefined t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop nop active nop read nop active nop t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t ck
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 65 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 45: single read ? without auto precharge notes: 1. for this example, bl = 4, cl = 2, and the read burst is followed by a ?manual? precharge. 2. x16: a9 and a11 = ?don?t care.? x32: a8, a9, and a11 = ?don?t care.? 3. precharge comman d not allowed or t ras would be violated. see table 17 on page 52. all banks t ch t cl t ac t lz t rp t ras t rcd cas latency t rc t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t cmh t cms nop nop nop precharge active nop read active nop disable auto precharge single banks don?t care undefined column m 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 dqmu, dqml cke clk a0?a9, a11 dq ba0, ba1 a10 command 3 3 t ck
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 66 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 46: single read ? with auto precharge notes: 1. for this example, bl = 4, cl = 2, and the read burst is followed by a ?manual? precharge. 2. x16: a9 and a11 = ?don?t care.? x32: a8, a9, and a11 = ?don?t care.? 3. precharge comman d not allowed or t ras would be violated. see table 17 on page 52. t ac enable auto precharge t ch t cl t rp t ras t rcd cas latency t rc dqmu, dqml cke clk a0?a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank t hz t oh d out m command t cmh t cms nop 3 read active nop nop 3 active nop t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 nop nop don?t care undefined t ck
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 67 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 47: alternating bank read accesses notes: 1. for this example, bl = 4 and cl = 2. 2. x16: a9 and a11 = ?don?t care.? x32: a8, a9, and a11 = ?don?t care.? see table 17 on page 52. enable auto precharge t ch t cl t ac t lz dqmu, dqml clk a0?a9, a11 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row row row t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop active nop read nop active t oh d out b t ac t ac read enable auto precharge row active row bank 0 bank 0 bank 3 bank 3 bank 0 cke t ckh t cks column m 2 column b 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 cas latency - bank 0 t rcd - bank 3 cas latency - bank 3 t t rc - bank 0 rrd t ck don?t care undefined
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 68 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 48: read ? full-page burst notes: 1. for this example, cl = 2. 2. x16: a9 and a11 = ?don?t care.? x32: a8, a9, and a11 = ?don?t care.? 3. page left open; no t rp. see table 17 on page 52. t ac t lz t rcd cas latency dqmu, dqml cke clk a0?a9, a11 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ac t oh d out m +1 row row t hz t ac t oh d out m +1 t ac t oh d out m +2 t ac t oh d out m -1 t ac t oh d out m full-page burst does not self-terminate. can use burst terminate command. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed 512 (x16) locations within same row command t cmh t cms nop nop nop active nop read nop burst term nop nop ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) t ah t as bank ( ) ( ) ( ) ( ) bank t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) column m 2 3 t0 t1 t2 t4 t3 t5 t6 tn + 1 tn + 2 tn + 3 tn + 4 don?t care undefined t ch t ck t cl
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 69 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 49: read ? dqm operation notes: 1. for this example, cl = 2. 2. x16: a9 and a11 = ?don?t care.? x32: a8, a9, and a11 = ?don?t care.? see table 17 on page 52. t ch t cl t rcd cas latency dqmu, dqml cke clk a0?a9, a11 dq ba0, ba1 a10 t cms row bank row bank t ac lz d out m t oh d out m + 3 d out m + 2 t t hz lz t t cmh command nop nop nop active nop read nop nop nop t hz t ac t oh t ac t oh t ah t as t cms t cmh t ah t as t ah t as t ckh t cks enable auto precharge disable auto precharge column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t ck don?t care undefined
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 70 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 50: write ? without auto precharge notes: 1. for this example, bl = 4, and the wri te burst is followed by a ?manual? precharge. 2. 15ns is required between and the precharge command regardless of fre- quency. 3. x16: a9 and a11 = ?don?t care.? x32: a8, a9, and a11 = ?don?t care.? see table 17 on page 52. disable auto precharge all banks t ch t cl t rp t ras t rcd t rc dqmu, dqml cke clk a0?a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank bank row row bank t wr d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write nop precharge active t ah t as t ah t as t dh t ds t dh t ds t dh t ds single bank t ckh t cks column m 3 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 nop don?t care undefined t ck
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 71 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 51: write ? with auto precharge notes: 1. for this example, bl = 4. 2. x16: a9 and a11 = ?don?t care.? x32: a8, a9, and a11 = ?don?t care.? see table 17 on page 52. enable auto precharge t ch t cl t rp t ras t rcd t rc dqmu, dqml cke clk a0?a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank row row bank t wr d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write nop active t ah t as t ah t as t dh t ds t dh t ds t dh t ds t ckh t cks nop nop column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 don?t care t ck
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 72 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 52: single write ? without auto precharge notes: 1. for this example, bl = 1, and the wri te burst is followed by a ?manual? precharge. 2. 15ns is required between and the precharge comma nd regardless of frequency. 3. x16: a9 and a11 = ?don?t care.? x32: a8, a9, and a11 = ?don?t care.? 4. precharge comman d not allowed or t ras would be violated. see table 17 on page 52. disable auto precharge all banks t ch t cl t rp t ras t rcd t rc d qmu, dqml cke clk a0?a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row bank bank bank row row bank t wr d in m t dh t ds command t cmh t cms nop 4 nop 4 precharge active nop write active nop nop t ah t as t ah t as single bank t ckh t cks column m 3 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 don?t car e t ck
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 73 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 53: single write ? with auto precharge notes: 1. for this example, bl = 1, and the wri te burst is followed by a ?manual? precharge. 2. 15ns is required between and the precharge command , regardless of frequency. 3. x16: a9 and a11 = ?don?t care.? x32: a8, a9, and a11 = ?don?t care.? 4. write command not allowed or t ras would be violated. see table 17 on page 52. enable auto precharge t ch t cl t rp t ras t rcd t rc dqmu, dqml cke clk a0?a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank row row bank t wr d in m command t cmh t cms nop 3 nop 3 nop active nop 3 write nop active t ah t as t ah t as t dh t ds t ckh t cks nop nop column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 don?t care t ck
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 74 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 54: alternating bank write accesses notes: 1. for this example, bl = 4. 2. x16: a9 and a11 = ?don?t care.? x32: a8, a9, and a11 = ?don?t care.? see table 17 on page 52. don?t care t ch t cl clk dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop active nop write nop nop active t dh t ds t dh t ds t dh t ds active write d in b t dh t ds d in b + 1 d in b + 3 t dh t ds t dh t ds enable auto precharge dqmu, dqml a0?a9, a11 ba0, ba1 a10 t cmh t cms t ah t as t ah t as t ah t as row row row row enable auto precharge row row bank 0 bank 0 bank 1 bank 0 bank 1 cke t ckh t cks d in b + 2 t dh t ds column b 2 column m 2 t t ras - bank 0 t rcd - bank 0 t t rcd - bank 0 t wr - bank 0 wr - bank 1 t rcd - bank 1 t t rc - bank 0 rrd t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t ck rp - bank 0
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 75 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 55: write ? full-page burst notes: 1. x16: a9 and a11 = ?don?t care.? x32: a8, a9, and a11 = ?don?t care.? 2. t wr must be satisfied pr ior to prechar ge command. 3. page left open; no t rp. see table 17 on page 52. t rcd dqmu, dqml cke clk a0?a9, a11 ba0, ba1 a10 t cms t ah t as t ah t as row row full-page burst does not self-terminate. can use burst terminate command to stop. 2, 3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed don?t care command t cmh t cms nop nop nop active nop write burst term nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 t dh t ds t dh t ds t dh t ds d in m - 1 t dh t ds t ah t as bank ( ) ( ) ( ) ( ) bank t cmh t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 512 (x16) locations within same row column m 1 t0 t1 t2 t3 t4 t5 tn + 1 tn + 2 tn + 3 t ch t cl t ck
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 76 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram timing diagrams figure 56: write ? dqm operation notes: 1. for this example, bl = 4. 2. x16: a9 and a11 = ?don?t care.? x32: a8, a9, and a11 = ?don?t care.? see table 17 on page 52. don?t care t rcd dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cms t ah t as row bank row bank enable auto precharge d in m + 3 t dh t ds d in m d in m + 2 t cmh command nop nop nop active nop write nop nop t cms t cmh t dh t ds t dh t ds t ah t as t ah t as disable auto precharge t ckh t cks column m 2 t0 t1 t2 t3 t4 t5 t6 t7 t ch t cl t ck
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 77 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram package dimensions package dimensions figure 57: 54-ball fbga, ?f4/b4 ? package (x16 device), 8mm x 8mm notes: 1. all dimensions are in millimeters. 2. recommended pad size for pcb is 0.40mm. 3. topside part marking decoder can be found at h ttp://www.micron.co m/support/fbga/ decoder.aspx. ball a1 id 0.65 0.05 seating plane 0.10 c c 1.00 max ball a9 0.80 typ 0.80 typ 3.20 6.40 8.00 0.10 4.00 0.05 solder ball diameter refers to post reflow condition. the pre- reflow diameter is 0.42. 54x ?0.45 0.05 solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn, 3% ag, 0.5% cu solder mask defined ball pads: ?0.40 mold compound: epoxy novolac substrate material: plastic laminate 6.40 3.20 4.00 0.05 8.00 0.10 c l c l ball a1 id ball a1
pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 78 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram package dimensions figure 58: 90-ball fbga, ?f5/b5 ? package (x32 device), 8mm x 13mm notes: 1. all dimensions are in millimeters. 2. recommended pad size for pcb is 0.4mm 0.025mm. 3. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 4. topside part marking decoder can be found at h ttp://www.micron.co m/support/fbga/ decoder.aspx. ball a1 id 1.00 max mold compound: epoxy novolac substrate material: plastic laminate solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn, 3%ag, 0.5% cu 13.00 0.10 ball a1 ball a9 ball a1 id 0.80 typ 6.50 0.05 8.00 0.10 4.00 0.05 3.20 5.60 0.05 0.65 0.05 seating plane a 11.20 0.10 6.40 0.10 a 90x ?0.45 dimensions apply to solder balls post reflow. the pre- reflow diameter is 0.42 on a 0.40 smd ball pad c l c l
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits spec ified over the power supply an d temperature range set forth herein. although considered final, these specifications ar e subject to change, as furthe r product development and data characterization sometimes occur. 128mb: x16, x32 mobile sdram package dimensions pdf: 09005aef807f4885/source: 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. l 10/07 en 79 ?2001 micron technology, inc. all rights reserved. figure 59: 54-pin plastic tsop (400 mil) notes: 1. all dimensions are in millimeters. 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. see detail a 0.80 typ 0.71 10.16 0.08 0.50 0.10 pin #1 id detail a 22.22 0.08 0.375 0.075 1.2 max 0.10 0.25 11.76 0.20 0.80 typ 0.15 +0.03 -0.02 0.10 +0.10 -0.05 gage plane plastic package material: epoxy novolac lead finish: tin/lead plate package width and length do not include mold protrusion. allowable protrusion is 0.25 per side.

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